aarch64 sdm

Part A ARMv8 Architecture Introduction and Overview

Part B The AArch64 Application Level Architecture

Chapter B1 The AArch64 Application Level Programmers’ Model

Chapter B2 The AArch64 Application Level Memory Model

C

C3.2.2 Load/Store register (unscaled offset)

Part D The AArch64 System Level Architecture

This chapter describes the AArch64 system level programmers’ model. It contains the following sections:

• Exception levels on page D1-1850.
• Exception terminology on page D1-1851.
• Execution state on page D1-1853.
• Security state on page D1-1854.
• Virtualization on page D1-1856.
• Registers for instruction processing and exception handling on page D1-1859.
• Process state, PSTATE on page D1-1865.
• Program counter and stack pointer alignment on page D1-1868.
• Reset on page D1-1870.
• Exception entry on page D1-1874.
• Exception return on page D1-1883.
• The Exception level hierarchy on page D1-1887.
• Synchronous exception types, routing and priorities on page D1-1894.
• Asynchronous exception types, routing, masking and priorities on page D1-1902.
• Configurable instruction enables and disables, and trap controls on page D1-1910.
• System calls on page D1-1953.
• Mechanisms for entering a low-power state on page D1-1954.
• Self-hosted debug on page D1-1959.
• The Performance Monitors Extension on page D1-1961.
• Interprocessing on page D1-1962.
• The effect of implementation choices on the programmers’ model on page D1-1974.

Part I Memory-mapped Components of the ARMv8 Architecture

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