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Historical Perspective and Reference

M.1 Itroduction

Those who can not remember past are condemned to repeat it.

Content M Section
invention 2 1
memory 3 2 B
ISA 4 A J K
Pipeline 5 3 C H
data-level parallelism 6 4
multiprocessor 7 5 F G I
cluster 8 6
IO 9 D

7(DSP) E(embedded) L(unknowd)

M.2 The early developement of Computers

digital computers

performance measurement

mercury delay line

Harvard Architecture

instruction time -> mix instruction time -> MIPS -> relative MIPS -> MFLOPS -> SPEC

M.3 The development of Memory Hierarchy and Protection

Virtual memory

cache:

  1. direct-mapped cache
  2. spatial locality and temporal locality
  3. nonblocking cache
  4. prefetching

M.4 The Evolution of Instruction Sets

stack architecture

VAX

RISC

M.5 The Development of Pipelining and Instruction-Level Parallelism

Dynamic Scheduling

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