Instruction-Level Parallelism and it’s Exploitation

3.4 Overcoming Data Hazard With Dynamic Scheduling

3.5 Dynamic Scheduling: Example and the Algorithm

The narration is bad can not understand it at all. There is some linkes for smoother learn curve.

  1. https://github.com/Milleraj66/ECE585_TomasuloAlgorithm.git
  2. https://github.com/GodTamIt/tomasulo-simulation
  3. https://en.wikipedia.org/wiki/Tomasulo_algorithm#Implementation_concepts
  4. http://nathantypanski.github.io/tomasulo-simulator/

notes from wiki:

  1. Tomasulo’s algorithm is a computer architecture hardware algorithm for dynamic scheduling of instructions that allows out-of-order execution and enables more efficient use of multiple execution units
  2. The placeholder value is a tag indicating which reservation station will produce the real value. When the unit finishes and broadcasts the result on the CDB, the placeholder will be replaced with the real value.
  3. Each functional unit has a single reservation station

3.6 Hardware-Based Speculation

Hardware-based speculation combines three key ideas:

  1. dynamic branch prediction to choose which instructions to execute,
  2. speculation to allow the execution of instructions before the control dependences are resolved (with the ability to undo the effects of an incorrectly speculated sequence), and
  3. dynamic scheduling to deal with the scheduling of different combinations of basic blocks. (In comparison, dynamic scheduling without speculation only partially overlaps basic blocks because it requires that a branch be resolved before actually executing any instructions in the successor basic block.)

The key idea behind implementing speculation is to allow instructions to execute out of order but to force them to commit in order and to prevent any irrevocable action (such as updating state or taking an exception) until an instruction commits

the ROB supplies operands in the interval between completion of instruction execution and instruction commi

3.7 Exploiting ILP Using Multiple Issue and Static Scheduling

The goal of the multiple-issue processors, discussed in the next few sections, is to allow multiple instructions to issue in a clock cycle. Multiple-issue processors come in three major flavors:

  1. Statically scheduled superscalar processors
  2. VLIW (very long instruction word) processors
  3. Dynamically scheduled superscalar processors

The two types of superscalar processors issue varying numbers of instructions per clock and use in-order execution if they are statically scheduled or out-of-order execution if they are dynamically scheduled

copy the P219 table

3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation

Two different approaches have been used to issue multiple instructions per clock in a dynamically scheduled processor, and both rely on the observation that the key is assigning a reservation station and updating the pipeline control tables. One approach is to run this step in half a clock cycle so that two instructions can be processed in one clock cycle A second alternative is to build the logic necessary to handle two or more instructions at once, including any possible dependences between the instructions

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