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内核文档

内核文档

While the IOMMU may be able to distinguish between devices within the enclosure, the enclosure may not require transactions between devices to reach the IOMMU.

Examples of this could be anything from a multi-function PCI device with backdoors between functions to a non-PCI-ACS (Access Control Services) capable bridge allowing redirection without reaching the IOMMU. Topology can also play a factor in terms of hiding devices. A PCIe-to-PCI bridge masks the devices behind it, making transaction appear as if from the bridge itself. Obviously IOMMU design plays a major factor as well.

https://docs.redhat.com/en/documentation/red_hat_enterprise_linux/7/html/virtualization_deployment_and_administration_guide/sect-iommu-deep-dive#sect-iommu-deep-dive

This is the reason why a typical x86 PC will group all conventional-PCI devices together, with all of them aliased to the same requester ID, the PCIe-to-PCI bridge.

An Introduction to IOMMU Infrastructure in the Linux Kernel

参考

ccw

https://www.kernel.org/doc/html/latest/driver-api/vfio.html https://www.kernel.org/doc/html/latest/driver-api/vfio-mediated-device.html https://zhuanlan.zhihu.com/p/27026590

https://kernelnote.com/iommu-posted-interrupt-deep-dive.html

iommu 硬件上是通过 capability register(CAP_REG) 当中的PI这个field来表示其是否支持 posted interrupt,具体的格式如下

(不能确认) 不知道这个图哪里搞的

drivers/iommu/intel/irq_remapping.c

		if (boot_cpu_has(X86_FEATURE_CX16))
			intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;

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